GaNonCMOS is a research and innovation project funded by the European Union’s Horizon 2020 program and coordinated by the Catholic University of Leuven. Its full title is “GaN densily integrated with Si-CMOS for reliable, cost effective frequency power delivery systems”.
The overall objective of the project is to develop novel low cost and reliable GaN-based process, components, modules and integration schemes, and demonstrate their performance and economic potential on system level for significant energy reduction in a wide range of energy intensive applications.
The GaNonCMOS project aims to bring GaN power electronic systems to the next level of maturity by providing the most densely integrated systems to date. The key innovations steps are:
- Long term reliability improvements over the full value chain of materials, devices, modules and systems with consortium partners that cover the entire value chain.
- Develop new soft magnetic core materials reaching switching frequencies up to 300 MHz with ultralow power losses to be integrated at different levels.
- New materials and methods for miniaturized packages to allow GaN devices, modules and systems to operate under maximum speed and energy efficiency.
- Integrate GaN power switches with CMOS drivers densely together using 3 different integration schemes (see Fig.1) from the package level up to the chip level using wafer-bonding between GaN on Si(111) and CMOS on Si (100) wafers.
- Optimize the GaN materials stack and device layout to enable fabrication of normally-off devices for such low temperature integration processes (max 400oC).
The development of beyond the state-of-the-art materials in devices, modules and systems in GaNonCMOS will drive a new generation of densely integrated power electronics and pave the way toward low cost, highly reliable systems for energy intensive applications.
Power supply chains in many electronic applications consist of multiple stages of AC-DC and DC-DC voltage converter modules and power interconnects, from the main AC supply to the C4 connectors on the electronic boards for the data centers and automotive examples. A point of load (PoL) VRM provides a point of load with the appropriate supply voltage, like converting 12 V to a much lower voltage (e.g. 1V), as required by a CPU, close to the final load. In the context of IT applications, VRM differs in specifications, topology and design depending upon the specific computing application considered: mainframe servers, cloud computing systems, mobile applications etc. Most significantly, the voltage and current rating for each application determines the structure and design of the VRM.
The loss of efficiency in a power supply chain in all applications arises mainly from the following two sources:
- Loss in the VRM during the voltage down-conversion
- IR losses in the power interconnects across the PCB
Losses in the VRM can be reduced by minimizing the number of stages of voltage conversion along the power supply chain. This requires efficient large voltage-ratio converters. While VRM efficiency is a complex function of its design, subcomponent characteristics and operating conditions, its efficiency drops with increasing voltage conversion ratios- a challenge that must be overcome with innovation in materials, improved design and by increasing operating frequencies. IR losses are minimized either by reducing electrical resistance along the power supply chain via increasing the number of power interconnects to the CPU or by bringing the PoL conversion as close as possible to the CPU, thereby reducing the currents in the long power interconnects across the PCB.
In addition, energy-efficient operation of a typical multi-core CPU entails the dynamic voltage and frequency scaling (DVFS) of the various cores and other logic components of the CPU. Fast voltage scaling in MHz frequencies can result in energy savings up to 40-60%. Hence, a highly granular multiple voltage domains power supply whose output voltages can be dynamically varied is needed for improving the overall energy efficiency of the entire computing system.
Therefore, the ideal power converter for these applications consists of an efficient, compact, granular, large voltage ratio power converter situated as close as possible to the PoL and has a wide dynamic operating range. This will be realized by integrating GaN power switches with CMOS drivers densely together using different integration schemes from the package level up to the chip level including wafer bonding between GaN on Si(111) and CMOS on Si (100) wafers.
The GaNonCMOS activities are organized into seven work packages, whose main objectives and activities are summarized below.
Arrive at a design for the VRM system, the power transistors, the magnetic components and the CMOS control chip for the Package level, Stack level and Chip level demonstrators.
Development of new magnetic materials and processes to deposit such materials for application in high frequency magnetic cores, development of GaN-on-Si epiwafer material and processes to fabricate such epiwafers, for application in HF GaN switches, and finally investigate several exploratory GaN process steps to support the development of the next generation GaN switches.
Define the specifications for each VRM demonstrator, fabricate the package-, stack and chip-level VRM demonstrators, perform functional testing and bring them up in the final application/industrial environment.
Promote the up-scale and use of the newly developed demonstrators and technologies amongst specifically identified European and International companies as well as provide opportunities for these stakeholders to deliver feedback on the project results to identify future collaboration. Facilitate a short time to market of the project results. Design and execute an effective dissemination and communication strategies for the benefit of the European industry, the European research area, and the public at large.